[back]

Optically Programmable FPGA Systems
Jose Mumbru, George Panotopoulos, Arrigo Benedetti, Demetri Psaltis, Pietro Perona Industrial Collaborators: Holoplex, Honeywell, Photobit

Abstract. The aim of this project is to investigate and demonstrate a Parallel Optical Interface between a Holographic Memory and a Silicon Circuit. This interface is implemented as an Optical Programmable Gate Array (OPGA), which is an enhanced version of a conventional FPGA, utilizing a holographic memory accessed by an array of VCSELs to program its logic. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module is very compact and has extremely short configuration time allowing for dynamic reconfiguration. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and searches in databases. The silicon hardware used for the OPGA can also be interfaced to a Holographic Disk Database and used for fast searches in the stored data.

Motivation. Initial motivation for the OPGA project came from the field of Reconfigurable Computing. Reconfigurable processors make possible to use more efficiently their resources by adjusting themselves depending on the characteristics of the input or on non-satisfactory previous results to better implement the target task. Given an application, like pattern recognition, the reconfigurable processor can be customized to deal with a specific class of objects. It can adapt itself in order to be robust to changes of orientation or illumination of the input object. By reprogramming, the same hardware can be time-multiplexed to carry out sequentially several tasks on the same input, or perform different task to different parts of the same input image. Reconfiguration also possibilities to implement learning by allowing the processor evolve in a controlled manner to learn the function that needs to be computed.

Figure 1. Reconfigurable processor for pattern recognition.

A Field Programmable Gate Array (FPGA) is a device where this idea of reconfigurable hardware can be implemented. FPGAs emerged as a new technology for the implementation of digital logic circuits during mid 80's. The basic architecture of an FPGA consists of a large number of configurable logic elements and a programmable mesh of interconnections. These devices are configured by static RAM (SRAM). The volatility of SRAM-based FPGAs, rather than being a problem, opens a new spectrum of applications because the programming of the device can be changed electrically at almost any point during operation. An important issue to be considered is the FPGA configuration time. Configuration of most of current FPGA's is performed serially shifting a very long bit stream into the device, a process that can take in the range of tens, up to a few hundreds, of milliseconds. An attempt to try to reduce this configuration time consists of implementing a cache memory in the FPGA capable of holding a few extra different configurations. Although the reconfiguration time is fairly reduced, this solution presents some drawbacks like the overhead in area that has to be dedicated to SRAM cells instead of logic elements, and the increase in power dissipation when switching between configurations. To overcome these problems we will use a holographic memory to store FPGA configuration templates and optically reconfigure the device by reading out the appropriate hologram. The main advantages of this approach are the following:

1. Using optics for reconfiguring the FPGA, the configuration template stored as a hologram is read out all at once and loaded in parallel into the chip using an array of detectors. This makes possible to decrease reconfiguration times by several orders of magnitude.

2. A holographic memory can store hundreds of different configurations, which means a two-order of magnitude increase over proposed time-multiplexed FPGA's.

3. Bringing the reconfiguration data storage and control logic off chip, the logic density of the FPGA can be increased.

Research. Based on this FPGA architecture, the OPGA is a device where the computation is still performed by programmable logic blocks and interconnects as in the conventional FPGA, but where the reconfiguration is brought into the chip optically. This optical reconfiguration capability results from interfacing an optical or holographic memory with a Silicon chip where, in addition to the logic resources, an array of photodetectors is incorporated. The holographic memory can store a large number of configuration templates that can be transferred down to the logic in the FPGA chip in a page-oriented mode.

Figure 2. Optically Programmable Gate Array.

Figure 3. Optically Addressable Look-Up Table.

The OPGA is basically the integration of three main components or technologies: an addressing mechanism, implemented either by an array of MEMS or an array of VCSELs used to retrieve the templates stored in the memory; the optical memory that contains a large set of configuration contexts; and the VLSI chip that combines CMOS logic and photodetectors.

In its initial implementation, the OPGA module is intended to operate as a Holographic Read-Only Memory (HROM), where a priori and for a given application, the user will decide the library of different configuration templates that need to be stored in the memory. This eliminates all the optics and optoelectronics required to write in the memory, like a spatial light modulator, and makes the OPGA module very compact. The technique used to store the holograms in the memory combines both spatial and shift multiplexing. The reason for such choice is the low power emitted by the VCSELs, which makes necessary to redesign the OPGA module in order to still have short reconfiguration times, in the range of tens of microseconds, but with a not so demanding requirement on the power per VCSEL.

Upon recording, a lens focuses the beam that impinges the SLM down to a small spot on the recording medium. By changing the angle of incidence of the beam on the lens, the signal spot focuses on a different location in the material, which is partially overlapping with the previous ones. The pages of data are recorded in these partially overlapping circles that span a stripe on the optical material. To achieve Bragg mismatch among holograms, a converging reference beam needs to be shifted accordingly to illuminate the corresponding signal spot. In the recording setup, a laser diode with enough coherence length can be used instead of the VCSEL array. The beam emitted by the diode is collimated and spited into the signal and reference arm. The signal beam passes through a rotation stage and a 4-F system that changes its angle before it illuminates the SLM. The reference beam is focused by a lens mounted on a mechanical scanner used to translate the beam beyond the shift-selectivity of the optical medium.

Figure 4. OPGA recorder.

Figure 5. OPGA reader.

During readout, the system becomes very compact because of two reasons. First, we use reflection geometry for recording, so upon readout the reading beam from the VCSEL and the array of photodetectors are both located on the same side of the material. Secondly, phase-conjugate readout makes unnecessary the use of any extra component. Placing the VCSEL array at the plane where the converging reference beams used for recording focus, each VCSEL illuminates one of the spots in the memory and all the reconstructed images back-propagate to the plane of the SLM where the photodetector array is upon readout.

As benefit from this architecture, we obtain an important increase in the diffraction efficiency per hologram, which now scales not as the total number of stored holograms but the number of overlapping ones at any location. So, for a system dealing with 100 configuration pages, 320 microwatts per VCSEL would be enough to reconfigure in just 20 microseconds. Another advantage of this architecture is that the total area used on the recording medium is small. If the lens that focuses the signal beam has a focal length of 10mm, the signal spot size on the material is just 2.7mm in diameter and 100 holograms can be stored on a stripe 2.7mm wide by 16mm long. Given the small dimensions of the area where the pages are recorded, the holograms are much less sensitive to any non-uniformity on the medium and, consequently, the quality of the reconstructed images is better.

Achievements. At this point we have obtained results both in the design and characterization of individual components, as well as their integration. Regarding addressing devices arrays of VCSELs provided by Honeywell have been tested and characterized to verify if this type of laser diodes is suitable for holographic recording. These VCSELs lasing in the red region of the spectrum around 680nm. In our system, the VCSELs need to operate in single mode in order to have uniform reconstruction of the holograms and to guarantee low reconfiguration times the output power should be at least 0.5mW per element. Another important requirement is the wavelength uniformity across the entire array, which should be within 0.05% uniformity.

Figure 6. VCSEL array.


Figure 7. Wavelength.

The last generation of VCSELs, rows of 25 elements, comply with the above mentioned wavelength and power specifications and they have been mounted together with multiplexors in a single package.

MEMS micromirror arrays have been investigated as an alternative addressing device. We have been able to record multiplexed holograms using such an array, and its use could potentially remedy several of the VCSELs limitations.

Figure 8. Hologram Multiplexing using MEMS.

Another important issue is to consider which optical medium is the best match for the OPGA system. A number of holographic materials have been investigated, like Du Pont photopolymer, LiNbO3:Fe crystals, and PVA-Mb films among others. Aprilis material has been characterized and selected for this project due to its excellent properties. This material presents large dynamic range, very low shrinkage and high optical quality.

Figure 9. Multiplexing experiment in Aprilis.


Figure 10. Image plane hologram in Aprilis.

As far as the OPGA chip is concerned, three generations of chips have been designed and fabricated in collaboration with Photobit. The OPGA chip integrates both an array of active pixel sensors (APS) to detect the hologram and the customizable logic in the form of look-up tables and interconnection matrices. In order to be more robust in front of the intensity non-uniformity inherent to the hologram differential detectors are used. In this coding scheme, each configuration bit corresponds to a pair of pixels in the hologram.

Figure 11. Full OPGA chip.

Figure 12. Customizable logic.

The logic in the OPGA chip can be programmed either electronically, as in a conventional FPGA, or optically by using the APS array. As a preliminary step, the chip was interfaced and pixel-matched to a spatial light modulator that can project different pattern onto the APS array. This patterns are used to test the APS array and to program in a number of different ways the on-chip logic. In a separate experiment the response of the chip vs. different light intensities was measured.

A simple demonstrator helps us to show that it is possible to build a compact OPGA module. For this demo, a 1x5 VCSEL array has been used to readout two holograms that had been stored in the optical memory, in this case a 100-micron thick layer of Du Pont photopolymer. Instead of the OPGA chip, a simple CCD camera has been used to display on a monitor the different pages of data. The module is mounted on a board contain the driver for the VCSELs and some circuitry to determine the sequence of activation of the VCSELs in the array. The whole system can be powered with 9-volt batteries.

Figure 13. OPGA module.

Figure 14. OPGA board.

During recording, a laser diode is used. The VCSEL array is pulled off the model and the laser beam of the diode is positioned to record the two holograms in the optical medium. Once the recording is finished the VCSEL array is inserted back into the model and the module is ready to operate.

Finally the OPGA chip was interfaced to a holographic memory and different configurations were successfully programmed onto the chip. This last experiment demonstrates the feasibility of transferring information in parallel from a holographic database to a silicon chip.

Figure 15. Holographic memory to chip interface.




Figure 16. Hologram of pattern used for programming.

Figure 17. Oscilloscope trace of programmed chip.

Related Links. Another important area of research is to develop applications that can benefit from the unique properties of the OPGA. Such applications can now make use not only of the reconfigurability of the hardware but also of fast reconfiguration time.

One field where FPGAs have been successfully used is image processing and feature detection. By using the OPGA we could carry out much more complex real-time video processing. Further information on this application can be found in Real-Time Optical Flow Computation on a Reconfigurable Computer.

An example of how reconfigurable computers can more efficiently solve a given task is found in Divide and Conquer Strategy for Recognition, where the example of digit classification using neural networks is used to illustrate this point.

Publications/References

Optically Reconfigurable Processors. J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis. SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing, Vol. 74, pp. 265-288, Colmar, France, June 1999.

Optical memory for computing and information processing. J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis. Proc. SPIE on Algorithms, Devices, and Systems for Optical Information Processing III, Vol. 3804, p. 14-24, October 1999.

Optically Programmable Gate Array. J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, E. Fossum. Proc. SPIE of Optics in Computing 2000, Vol. 4089, p. 763-771, May 2000.